By Janusz Rajski
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Extra info for Arithmetic Built-In Self-Test for Embedded Systems
The waveforms and the center patterns they produce are also shown in Fig. 13. A key aspect of this generation scheme is how to extract a scan configuration from a given set of center patterns. To arrange scan cells properly, the center cubes are represented as an m x n matrix with rows corresponding to vectors and columns corresponding to successive inputs of the CUT. Many experiments indicate that three center deterministic patterns followed by spherical pseudo random patterns generated around them are sufficient to achieve very high fault coverage .
When α is a power of 2, independent LFSR stages fed into an AND gate produce the desired random signal. This signal is used to complement bits of the center test. The actual diffraction logic also includes additional flip-flops and gates to allow programming diffraction probabilities. This part of the diffractor is driven by the pattern counter and works as illustrated in the following example. 3. 5 Let us assume that a code 000 is stored in the flip-flops A, B, and C. As can be seen, a 1 can occur on the output of the diffractor with probability 1/16.
Similarly, sharing BIST circuitry, especially for regular structures of the same type though with nonidentical sizes, may significantly reduce the area overhead. This approach, however, can increase test application time, particularly when individual output data compaction is required. Contending with the problems just mentioned, and the desire to handle a fundamental trade-off between time and hardware as flexibly as possible, has cre ated two basic BIST execution options: parallel BIST or test-per-clock technique and serial BIST or test-per-scan approach.
Arithmetic Built-In Self-Test for Embedded Systems by Janusz Rajski